A low energy HEVC inverse transform hardware
- 1 November 2014
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Consumer Electronics
- Vol. 60 (4), 754-761
- https://doi.org/10.1109/tce.2014.7027352
Abstract
In this paper, a novel energy reduction technique for High Efficiency Video Coding (HEVC) Inverse Discrete Cosine Transform (IDCT) and Inverse Discrete Sine Transform (IDST) for all transform unit (TU) sizes is proposed. The proposed technique calculates IDCT and IDST only for DC coefficient if the values of several predetermined forward transformed low frequency coefficients in a TU are smaller than a threshold. The proposed technique reduces the computational complexity of IDCT and IDST significantly. It increases the bit rate slightly for most video frames. It decreases the PSNR slightly for some video frames, and it increases the PSNR slightly for some video frames. In this paper, a low energy HEVC 2D inverse transform (IDCT and IDST) hardware for all TU sizes is also designed and implemented using Verilog HDL. In the worst case, the proposed hardware can process 48 Quad HD (3840x2160) video frames per second. The proposed technique reduced the energy consumption of this hardware up to 32%. Therefore, the proposed hardware can be used in portable consumer electronics products that require a real-time HEVC encoder.Keywords
This publication has 15 references indexed in Scilit:
- A high performance deblocking filter hardware for high efficiency video codingIEEE Transactions on Consumer Electronics, 2013
- Complexity analysis of an HEVC decoder based on a digital signal processorIEEE Transactions on Consumer Electronics, 2013
- Comparative Rate-Distortion-Complexity Analysis of HEVC and AVC Video CodecsIEEE Transactions on Circuits and Systems for Video Technology, 2012
- HEVC Complexity and Implementation AnalysisIEEE Transactions on Circuits and Systems for Video Technology, 2012
- HEVC: The New Gold Standard for Video Compression: How Does HEVC Compare with H.264/AVC?IEEE Consumer Electronics Magazine, 2012
- Low Cost Design of a Hybrid Architecture of Integer Inverse DCT for H.264, VC-1, AVS, and HEVCVLSI Design, 2012
- Complexity control of high efficiency video encoders for power-constrained devicesIEEE Transactions on Consumer Electronics, 2011
- Adaptive Method for Early Detecting Zero Quantized DCT Coefficients in H.264/AVC Video EncodingIEEE Transactions on Circuits and Systems for Video Technology, 2008
- Multiplierless multiple constant multiplicationACM Transactions on Algorithms, 2007
- An improved early detection algorithm for all-zero blocks in H.264 video encodingIEEE Transactions on Circuits and Systems for Video Technology, 2005