Comprehensive performance re-assessment of TFETs with a novel design by gate and source engineering from device/circuit perspective
- 1 December 2014
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE) in 2014 IEEE International Electron Devices Meeting
- p. 13.3.1-13.3.4
- https://doi.org/10.1109/iedm.2014.7047044
Abstract
In this paper, a novel TFET design, called Pocket-mSTFET (PMS-TFET), is proposed and experimentally demonstrated by evaluating the performance from device metrics to circuit implementation for low-power SoC applications. For the first time, from circuit design perspective, TFETs performance in terms of I ON , I OFF , subthreshold slope (SS), output behavior, capacitance, delay, noise and gain are experimentally benchmarked and also compared with MOSFET. By gate and source engineering without area penalty, the compatibly-fabricated PMS-TFET on SOI substrate shows superior performance with the minimum SS of 29mV/dec at 300K, high I ON (~20μA/μm) and large I ON /I OFF ratio (~10 8 ) at 0.6V. Largely alleviated super-linear onset issue, reduced Miller capacitance and delay, and much lower noise level were also experimentally obtained, as well as high effective gain. Circuit-level implementation based on PMS-TFET also shows significant improvement on energy efficiency and power reduction at V DD of 0.4V, which indicates great potential of this TFET design for low-power digital and analog applications.Keywords
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