SOI for a 1-volt CMOS technology and application to a 512 Kb SRAM with 3.5 ns access time
- 30 December 2002
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 813-816
- https://doi.org/10.1109/iedm.1993.347275
Abstract
In this paper a CMOS technology that is optimum for low voltage (in the I-volt range) applications is presented. Thin but undepleted SOI is used as the substrate, which gives low junction capacitance and no body effect. Furthermore floating body effects causes a reduction of subthreshold slope at high drain bias. This lowers the high-V/sub DS/ threshold to be used, which increases the current drive without significant increase in the off-current. This technology was applied to a high performance 512 Kb SRAM. Access time of 3.5 ns at 1 V was obtained.Keywords
This publication has 2 references indexed in Scilit:
- A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architectureIEEE Journal of Solid-State Circuits, 1991
- A 1 V operating 256-Kbit full CMOS SRAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1990