Refresh pausing in DRAM memory systems
- 1 February 2014
- journal article
- Published by Association for Computing Machinery (ACM) in ACM Transactions on Architecture and Code Optimization
- Vol. 11 (1), 1-26
- https://doi.org/10.1145/2579669
Abstract
Dynamic Random Access Memory (DRAM) cells rely on periodic refresh operations to maintain data integrity. As the capacity of DRAM memories has increased, so has the amount of time consumed in doing refresh. Refresh operations contend with read operations, which increases read latency and reduces system performance. We show that eliminating latency penalty due to refresh can improve average performance by 7.2%. However, simply doing intelligent scheduling of refresh operations is ineffective at obtaining significant performance improvement. This article provides an alternative and scalable option to reduce the latency penalty due to refresh. It exploits the property that each refresh operation in a typical DRAM device internally refreshes multiple DRAM rows in JEDEC-based distributed refresh mode. Therefore, a refresh operation has well-defined points at which it can potentially be Paused to service a pending read request. Leveraging this property, we propose Refresh Pausing , a solution that is highly effective at alleviating the contention from refresh operations. It provides an average performance improvement of 5.1% for 8Gb devices and becomes even more effective for future high-density technologies. We also show that Refresh Pausing significantly outperforms the recently proposed Elastic Refresh scheme.Keywords
This publication has 14 references indexed in Scilit:
- A case for Refresh Pausing in DRAM memory systemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2013
- RAIDRACM SIGARCH Computer Architecture News, 2012
- Characterization of the Variable Retention Time in Dynamic Random Access MemoryIEEE Transactions on Electron Devices, 2011
- Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density MemoryPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2010
- A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory HierarchiesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2008
- Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2007
- A Practical Approach to Exploiting Coarse-Grained Pipeline Parallelism in C ProgramsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2007
- Block-based multi-period refresh for energy efficient dynamic memoryPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips⋆Lecture Notes in Computer Science, 2001
- A performance comparison of contemporary DRAM architecturesACM SIGARCH Computer Architecture News, 1999