Extreme Thinning of Si Wafers for Via-Last and Multi-wafer Stacking Applications

Abstract

3D-System-On-Chip (3D-SoC) technology schemes will require more and more wafer-to-wafer bonding combined with extreme wafer thinning and via-last TSV (Through Silicon Vias) connections. In this work, we focus on the thinning process to target a top wafer thickness in the 5μm range with a very tight thickness control. Wafer thinning is performed by subsequently back-grinding, Si CMP and Si dry etch based on an in-situ NIR (near-infrared) end-point detection system. Optimization of the dry etch process has been performed by looking into various chamber configurations in order to minimize the Si thickness profile variations. A detailed characterization of the thin Si profile was done by using dedicated metrology tools, and special attention has been given to the wafer edge inspection.