In-line metrology for characterization and control of extreme wafer thinning of bonded wafers

Abstract

The pace of innovation in device packaging techniques has never been faster and more interesting as nowadays. Previously, data were sent through wires where in recent packages, components are connected directly using different 3D interconnect technologies. As the 3D interconnect density is increasing exponentially, pitches need to reduce. Current interconnect technologies of 3D-Stacked IC, do not offer such high densities. Parallel front-end of line wafer processing in combination with wafer-to-wafer bonding and extreme wafer thinning steps in the 3D System On Chip integration technology schemes enable the increase of 3D interconnect density. During the extreme wafer thinning process pathfinding and development, different thinning techniques were evaluated to target a final Si thickness specification. In this paper, metrology use cases are demonstrated and elaborated that were applied in this pathfinding and development phase. These metrology tools supplied results that enabled us to determine where the extreme wafer thinning process can be improved. The same techniques can eventually be used to validate the improvements and to monitor process stability when processes are released for volume production.