A Tunnel FET for $V_{DD}$ Scaling Below 0.6 V With a CMOS-Comparable Performance
- 12 May 2011
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 58 (7), 1855-1863
- https://doi.org/10.1109/ted.2011.2140322
Abstract
We propose a modified structure of tunnel field-effect transistor (TFET), called the sandwich tunnel barrier FET (STBFET). STBFET has a large tunneling cross-sectional area with a tunneling distance of ~2 nm. An orientation-dependent nonlocal band-to-band tunneling (BTBT) model was employed to investigate the device characteristics. The feasibility of the STBFET realization using a complementary metal-oxide-semiconductor-compatible process flow has been shown using advanced process calibration with Monte Carlo implantation. STBFET gives a high I ON , exceeding 1 mA/μm at I OFF of 0.1 pA/μm with a subthreshold swing below 40 mV/dec. The device also shows better static and dynamic performances for sub-1-V operations. STBFET shows a very good drain current saturation, which is investigated using an ab initio physics-based BTBT model. Furthermore, the simulated I ON improvement is validated through analytical calculations. We have also investigated the physical root cause of the large voltage overshoot of TFET inverters. The previously reported impact of Miller capacitance is shown to be of lower importance; the space-charge buildup and its relaxation at the channel drain junction are shown to be the dominant effect of large voltage overshoot of TFETs. The STBFET are shown to have negligible voltage overshoots compared with conventional TFETs.Keywords
This publication has 22 references indexed in Scilit:
- Si/SiGe Resonant Interband Tunneling Diodes Incorporating $\delta$-Doping Layers Grown by Chemical Vapor DepositionIEEE Electron Device Letters, 2009
- Drive current boosting of n-type tunnel FET with strained SiGe layer at sourceMicroelectronics Journal, 2008
- Strain-Engineered Si/SiGe Resonant Interband Tunneling Diodes Grown on $\hbox{Si}_{0.8}\hbox{Ge}_{0.2}$ Virtual Substrates With Strained Si Cladding LayersIEEE Electron Device Letters, 2008
- Effect of Low Temperature Annealing Prior to Non-melt Laser Annealing in Ultra-shallow Junction FormationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2007
- Double-Gate Tunnel FET With High-$\kappa$ Gate DielectricIEEE Transactions on Electron Devices, 2007
- On the Validity of the Parabolic Effective-Mass Approximation for the I–V Calculation of Silicon Nanowire TransistorsIEEE Transactions on Electron Devices, 2005
- Scaling the Vertical Tunnel FET With Tunnel Bandgap Modulation and Gate Workfunction EngineeringIEEE Transactions on Electron Devices, 2005
- Universal tunneling behavior in technologically relevant P/N junction diodesJournal of Applied Physics, 2004
- Predictive Monte Carlo ion implantation simulator from sub-keV to above 10 MeVJournal of Applied Physics, 2003
- A new analytical diode model including tunneling and avalanche breakdownIEEE Transactions on Electron Devices, 1992