Tunnel Transistors for Low Power Logic
- 1 October 2013
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
Tunnel transistor (TFET) as steep slope device to enable supply voltage scaling is explored at the device level as well as circuit level. Hetero-junction TFET is demonstrated with high drive current and high on-off current ratio. Hetero-junction TFETs with scaled device geometry outperform Si FINFET at Vcc <; 0.3V. Design considerations of TFET based circuits for logic applications are investigated and performance benchmarked with Si FinFET technology.Keywords
This publication has 8 references indexed in Scilit:
- Demonstration of improved heteroepitaxy, scaled gate stack and reduced interface states enabling heterojunction tunnel FETs with high drive current and high on-off ratioPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2012
- Tunnel field-effect transistors as energy-efficient electronic switchesNature, 2011
- An energy-efficient heterogeneous CMP based on hybrid TFET-CMOS coresPublished by Association for Computing Machinery (ACM) ,2011
- Self-aligned gate nanopillar In0.53Ga0.47As vertical tunnel transistorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2011
- Temperature-Dependent $I$– $V$ Characteristics of a Vertical $\hbox{In}_{0.53}\hbox{Ga}_{0.47}\hbox{As}$ Tunnel FETIEEE Electron Device Letters, 2010
- Modeling of High-Performance p-Type III–V Heterojunction Tunnel FETsIEEE Electron Device Letters, 2010
- Band-to-Band Tunneling in Carbon Nanotube Field-Effect TransistorsPhysical Review Letters, 2004
- Complementary tunneling transistor for low power applicationSolid-State Electronics, 2004