Hardware module selection for real time pipeline architectures using probabilistic cost estimation
- 24 December 2002
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE) in Proceedings Ninth Annual IEEE International ASIC Conference and Exhibit
- p. 147-150
- https://doi.org/10.1109/asic.1996.551981
Abstract
Module selection is a basic task of architectural synthesis which aims to optimize the cost of dedicated circuits. However, this task remains unresolved in the case of synthesizing pipeline architectures under real time constraint using a complex library exploiting multifunctional, pipeline, and multi-delay operators. This paper presents a new formalization and implementation of module selection integrated in the GAUT tool. The cost function used is based on the area of selected components and a probabilistic estimation of the area of registers, bus, and interconnections. It includes some results in the field of real time digital signal processing.Keywords
This publication has 6 references indexed in Scilit:
- Module selection for pipelined synthesisPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Automatic module allocation in high level synthesisPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- GAUT: An architectural synthesis tool for dedicated signal processorsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Probabilistic resource estimation for pipeline architecturePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Combined hardware selection and pipelining in high-performance data-path designIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1992
- Operators allocation in the silicon compiler SCOOPIntegration, 1989