Probabilistic resource estimation for pipeline architecture
- 19 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE) in VLSI Signal Processing, VIII
Abstract
This paper presents a new approach to resource estimation in high level synthesis. Given a set of operators and a data flow graph specification, we apply a probability based method to compute the probable numbers of operators, registers, bus and operator connections for each time step or algorithm latency. Combined with statistical metrics, we obtain a quick and accurate estimation module that includes real precedence constraints. The aim of this work is to provide ASICs designers with a guidance tool for a better use of high level synthesis. Algorithm properties like dated resource concurrence and operator link statistics are computed to guide algorithmic, transformations and hardware selection Author(s) Diguet, J.P. LASTI-ENSSAT, Lannion, France Sentieys, O. ; Philippe, J.L. ; Martin, E.Keywords
This publication has 8 references indexed in Scilit:
- GAUT: An architectural synthesis tool for dedicated signal processorsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- System-level design guidance using algorithm propertiesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- How to specify an algorithm in VLSI architectural synthesis? A vocal coding applicationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Optimizing resource utilization using transformationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Combined hardware selection and pipelining in high performance data-path designPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Estimating implementation bounds for real time DSP application specific circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1994
- Estimating architectural resources and performance for high-level synthesis applicationsIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1993
- Predicting system-level area and delay for pipelined and nonpipelined designsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1992