An optimized Adder Accumulator for high speed MACs
- 6 April 2006
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 3 references indexed in Scilit:
- Speed-efficient wide adders for VIRTEX FPGAsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Accelerating pipelined integer and floating-point accumulations in configurable hardware with delayed addition techniquesIEEE Transactions on Computers, 2000
- A fast parallel multiplier-accumulator using the modified Booth algorithmIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 2000