An experimental study of data retention behavior in modern DRAM devices
- 23 June 2013
- conference paper
- conference paper
- Published by Association for Computing Machinery (ACM) in Proceedings of the 40th Annual International Symposium on Computer Architecture
Abstract
DRAM cells store data in the form of charge on a capacitor. This charge leaks off over time, eventually causing data to be lost. To prevent this data loss from occurring, DRAM cells must be periodically refreshed. Unfortunately, DRAM refresh operations waste energy and also degrade system performance by interfering with memory requests. These problems are expected to worsen as DRAM density increases. The amount of time that a DRAM cell can safely retain data without being refreshed is called the cell's retention time. In current systems, all DRAM cells are refreshed at the rate required to guarantee the integrity of the cell with the shortest retention time, resulting in unnecessary refreshes for cells with longer retention times. Prior work has proposed to reduce unnecessary refreshes by exploiting differences in retention time among DRAM cells; however, such mechanisms require knowledge of each cell's retention time. In this paper, we present a comprehensive quantitative study of retention behavior in modern DRAMs. Using a temperature-controlled FPGA-based testing platform, we collect retention time information from 248 commodity DDR3 DRAM chips from five major DRAM vendors. We observe two significant phenomena: data pattern dependence, where the retention time of each DRAM cell is significantly affected by the data stored in other DRAM cells, and variable retention time, where the retention time of some DRAM cells changes unpredictably over time. We discuss possible physical explanations for these phenomena, how their magnitude may be affected by DRAM technology scaling, and their ramifications for DRAM retention time profiling mechanisms.Keywords
Funding Information
- Intel Corporation
- Division of Computing and Communication Foundations (CCF-0953246)
This publication has 27 references indexed in Scilit:
- RAIDRACM SIGARCH Computer Architecture News, 2012
- Random Telegraph Signal-Like Fluctuation Created by Fowler–Nordheim Stress in Gate Induced Drain Leakage Current of the Saddle Type Dynamic Random Access Memory Cell TransistorJapanese Journal of Applied Physics, 2010
- Si–H Bond Breaking Induced Retention Degradation During Packaging Process of 256 Mbit DRAMs With Negative Wordline BiasIEEE Transactions on Electron Devices, 2005
- Neighborhood pattern-sensitive fault testing and diagnostics for random-access memoriesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2002
- A low-impedance open-bitline array for multigigabit DRAMIEEE Journal of Solid-State Circuits, 2002
- Dynamic Memory Design for Low Data-Retention PowerLecture Notes in Computer Science, 2000
- On the retention time distribution of dynamic random access memory (DRAM)IEEE Transactions on Electron Devices, 1998
- Optimizing the DRAM refresh count for merged DRAM/logic LSIsPublished by Association for Computing Machinery (ACM) ,1998
- The impact of data-line interference noise on DRAM scalingIEEE Journal of Solid-State Circuits, 1988
- A meta-stable leakage phenomenon in DRAM charge storage —Variable hold timePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1987