High frequency CMOS amplifier with improved linearity
Open Access
- 1 November 2014
- journal article
- research article
- Published by Institution of Engineering and Technology (IET) in IET Circuits, Devices & Systems
- Vol. 8 (6), 450-458
- https://doi.org/10.1049/iet-cds.2013.0327
Abstract
In this paper, a novel amplifier linearisation technique based on the negative impedance compensation is presented. As demonstrated by using Volterra model, the proposed technique is suitable for linearising amplifiers with low open-loop gain, which is appropriate for RF/microwave applications. A single-chip CMOS amplifier has been designed using the proposed method, and the simulation results show that high gain accuracy (improved by 38%) and high linearity (IMD3 improved by 14 dB, OIP3 improved by 11 dB and adjacent channel power ratio (ACPR) improved by 44% for CDMA signal) can be achieved.Keywords
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