13.1 A 940MHz-bandwidth 28.8µs-period 8.9GHz chirp frequency synthesizer PLL in 65nm CMOS for X-band FMCW radar applications

Abstract

To obtain a 20cm-resolution image within a 15m distance using an X-band FMCW radar, an agile chirp frequency synthesizer phase-locked loop (FSPLL) with a wide chirp bandwidth (BW) greater than 750MHz and a short chirp period (Tm) less than 100μs is necessary. Challenges arise as one tries to realize a triangular chirp profile in Fig. 13.1.1 with a fast chirp slope (=BW/Tm) and precise linearity. In particular, many FMCW FSPLLs exhibit increased frequency errors around the turn-around points (TAPs), degrading the effective resolution achievable. For instance, for FSPLLs modulating either the reference or feedback clock frequency [1-3], the finite loop bandwidth of the PLL limits the maximum chirp slope as well as the linearity of the chirp profile. Moreover, many of these PLLs use a multi-modulus frequency divider (FD) and delta-sigma modulation (DSM) [2], which put further constraints on the maximum PLL bandwidth to filter the quantization noise. While a two-point modulation (TPM) scheme can decouple the conflicting requirements on the PLL bandwidth [4-6], the gain or timing mismatch between the two modulation paths and limited resolution of the DSM-based FD can still limit the chirp linearity, especially when one tries to push the chirp slope faster.