VIm-Scan: A Low Overhead Scan Design Approach for Protection of Secret Key in Scan-Based Secure Chips

Abstract

Scan-based DFT enhances the testability of a system by making its internal nodes more observable and controllable. However, in case of a secure chip, scan chain increases its vulnerability to attack, where the attacker can extract secret information by scanning out states of internal nodes. This paper presents VIm-Scan: a low overhead scan design methodology that maintains all the advantages of a traditional scan-based testing yet prevents secure key extraction through the scan out process. Experimental results show that the proposed approach entails significantly lesser design overhead (~5times reduction in number of additional gates) with comparable or better protection against attack than existing techniques.