A 3GHz Fractional-N All-Digital PLL with Precise Time-to-Digital Converter Calibration and Mismatch Correction

Abstract

This work introduces two techniques to ameliorate high-resolution TDC performance: a precise TDC calibration algorithm and a background mismatch correction algorithm. To demonstrate the proposed techniques we have realized a 3GHz fractional synthesizer based on an 8ps resolution TDC in standard 65nm CMOS. The prototype uses a 25MHz reference and consumes 9.5mW excluding test buffers. The bandwidth is programmable from 100kHz to 2MHz, in-band phase noise is -100dBc/Hz and the worst-case in-band spur, after correction, is -45dBc. This is the first prototype with low phase noise, spur suppression and wide-bandwidth known to the authors. Moreover, it is competitive with fractional-N analog PLLs.