Programmable Frequency-Divider for Millimeter-Wave PLL Frequency Synthesizers
- 1 October 2008
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE) in 2008 38th European Microwave Conference
Abstract
In this paper, a novel 4-modulus programmable frequency divider, suitable for millimeter wave PLL frequency synthesizer applications, is presented. The proposed frequency divider is designed using dynamic logic D flip-flop, and the divider is implemented in a standard 90 nm CMOS technology to achieve high frequencies of operation with very low power consumption. Measurements show a maximum input frequency of 3.5 GHz, and a power consumption of 4.5 mW from a 1.0 V supply. To the best knowledge of the authors, this divider shows one of the best figure of merit in terms of maximum speed of operation, low power consumption, and division ratio ranges for multi-GHz frequency dividers.Keywords
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