Optimization of Structure and Electrical Characteristics for Four-Layer Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices
Open Access
- 5 March 2021
- journal article
- research article
- Published by MDPI AG in Nanomaterials
- Vol. 11 (3), 646
- https://doi.org/10.3390/nano11030646
Abstract
In this paper, the optimizations of vertically-stacked horizontal gate-all-around (GAA) Si nanosheet (NS) transistors on bulk Si substrate are systemically investigated. The release process of NS channels was firstly optimized to achieve uniform device structures. An over 100:1 selective wet-etch ratio of GeSi to Si layer was achieved for GeSi/Si stacks samples with different GeSi thickness (5 nm, 10 nm, and 20 nm) or annealing temperatures (≤900 °C). Furthermore, the influence of ground-plane (GP) doping in Si sub-fin region to improve electrical characteristics of devices was carefully investigated by experiment and simulations. The subthreshold characteristics of n-type devices were greatly improved with the increase of GP doping doses. However, the p-type devices initially were improved and then deteriorated with the increase of GP doping doses, and they demonstrated the best electrical characteristics with the GP doping concentrations of about 1 × 1018 cm−3, which was also confirmed by technical computer aided design (TCAD) simulation results. Finally, 4 stacked GAA Si NS channels with 6 nm in thickness and 30 nm in width were firstly fabricated on bulk substrate, and the performance of the stacked GAA Si NS devices achieved a larger ION/IOFF ratio (3.15 × 105) and smaller values of Subthreshold swings (SSs) (71.2 (N)/78.7 (P) mV/dec) and drain-induced barrier lowering (DIBLs) (9 (N)/22 (P) mV/V) by the optimization of suppression of parasitic channels and device’s structure.Keywords
Funding Information
- the National Key Project of Science and Technology of China (2017ZX02301007-001 and 2017ZX02315001-001, Z201100006820084 and Z201100004220001, Y9YQ01R004 and Y2020037, E0YS01X001 and E0290X03)
- The National Natural Science Foundation of China (61904194 and 6187032253)
This publication has 21 references indexed in Scilit:
- Vertical Sandwich Gate-All-Around Field-Effect Transistors With Self-Aligned High-k Metal Gates and Small Effective-Gate-Length VariationIEEE Electron Device Letters, 2019
- GAA CNT TFETs Structural Engineering: A Higher ON Current, Lower AmbipolarityIEEE Transactions on Electron Devices, 2019
- Miniaturization of CMOSMicromachines, 2019
- FinFET With Improved Subthreshold Swing and Drain Current Using 3-nm Ferroelectric Hf0.5Zr0.5O2IEEE Electron Device Letters, 2019
- Influence of Rapid Thermal Annealing on Ge-Si Interdiffusion in Epitaxial Multilayer Ge0.3Si0.7/Si Superlattices with Various GeSi ThicknessesECS Journal of Solid State Science and Technology, 2018
- Physical Insights on Quantum Confinement and Carrier Mobility in Si, Si0.45Ge0.55, Ge Gate-All-Around NSFET for 5 nm Technology NodeIEEE Journal of the Electron Devices Society, 2018
- Stacked Ge-Nanosheet GAAFETs Fabricated by Ge/Si Multilayer EpitaxyIEEE Electron Device Letters, 2018
- Investigation on Electrostatic Discharge Robustness of Gate-All-Around Silicon Nanowire Transistors Combined With Thermal AnalysisIEEE Electron Device Letters, 2017
- Two methods of tuning threshold voltage of bulk FinFETs with replacement high-k metal-gate stacksSolid-State Electronics, 2017
- High-Performance Silicon Nanowire Gate-All-Around nMOSFETs Fabricated on Bulk Substrate Using CMOS-Compatible ProcessIEEE Electron Device Letters, 2010