Multilayer Si shadow mask processing of wafer-scale MoS2 devices

Abstract

Two-dimensional layered materials (2DLMs) have attracted great research interest due to their exotic physical properties and potential applications in nanoelectronics and optoelectronics. Device fabrication with 2DLMs is challenging because their ultrathin characteristic makes them extremely sensitive to the external environment, especially to chemical contamination introduced by optical lithography. The shadow mask technique is a clean alternative in lithography-free electrode patterning for emerging nanomaterials. However, shadow mask assisted fabrication over large areas and multilevel alignment of patterns remain challenging for practical applications. In this paper, we report an over wafer scale shadow mask fabrication technique for 2DLMs. Based on successful fabrication of customized silicon shadow masks with micrometer feature sizes, their advantages for fabricating higher mobility and lower interface trapped exfoliated MoS2 transistors are demonstrated. Meanwhile, applications in large-scale metal deposition and sample etching are also explored. The max alignment error of multilayer patterns fall in 0.5-3.0 mu m in x- and 2.0-9.0 mu m in y-directions. Then this technique is employed to realize a fabrication of MoS2 top-gated field effect transistor arrays with two universal strategies: 'etching-last' and 'channel-first' on 1 x 1 cm(2) Al2O3 substrate. Furthermore, logic inverter circuits with a high gain of 10 are successfully fabricated. The results provide an alternative as a universal, low-cost, time-saving method for fabricating large-scale 2DLM electronics and flexible electronics.