Morphable DRAM Cache Design for Hybrid Memory Systems
- 18 July 2019
- journal article
- research article
- Published by Association for Computing Machinery (ACM) in ACM Transactions on Architecture and Code Optimization
- Vol. 16 (3), 1-24
- https://doi.org/10.1145/3338505
Abstract
DRAM caches have emerged as an efficient new layer in the memory hierarchy to address the increasing diversity of memory components. When a small amount of fast memory is combined with slow but large memory, the cache-based organization of the fast memory can provide a SW-transparent solution for the hybrid memory systems. In such DRAM cache designs, their effectiveness is affected by the bandwidth and latency of both fast and slow memory. To quantitatively assess the effect of memory configurations and application patterns on the DRAM cache designs, this article first investigates how three prior approaches perform with six hybrid memory scenarios. From the investigation, we observe no single DRAM cache organization always outperforms the other organizations across the diverse hybrid memory configurations and memory access patterns. Based on this observation, this article proposes a reconfigurable DRAM cache design that can adapt to different hybrid memory combinations and workload patterns. Unlike the fixed tag and data arrays of conventional on-chip SRAM caches, this study advocates to exploit the flexibility of DRAM caches, which can store tags and data to DRAM in any arbitrary way. Using a sample-based mechanism, the proposed DRAM cache controller dynamically finds the best organization from three candidates and applies the best one by reconfiguring the tags and data layout in the DRAM cache. Our evaluation shows that the proposed morphable DRAM cache can outperform the fixed DRAM configurations across six hybrid memory configurations.Keywords
Funding Information
- Samsung Electronics
- Ministry of Science and ICT, Korea
- National Research Foundation of Korea (NRF-2019R1A2B5B01069816)
- Institute for Information and Communications Technology Promotion (IITP-2017-0-00466)
This publication has 31 references indexed in Scilit:
- A fully associative, tagless DRAM cachePublished by Association for Computing Machinery (ACM) ,2015
- BEARPublished by Association for Computing Machinery (ACM) ,2015
- Transparent Hardware Management of Stacked DRAM as Part of MemoryPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2014
- ATCachePublished by Association for Computing Machinery (ACM) ,2014
- Ultra‐wideband tapered slot antenna with dual band‐notched characteristicsIET Microwaves, Antennas & Propagation, 2014
- ZSimPublished by Association for Computing Machinery (ACM) ,2013
- Die-stacked DRAM caches for serversPublished by Association for Computing Machinery (ACM) ,2013
- Fundamental Latency Trade-off in Architecting DRAM Caches: Outperforming Impractical SRAM-Tags with a Simple and Practical DesignPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2012
- Fair Queuing Memory SystemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2006
- SPEC CPU2006 benchmark descriptionsACM SIGARCH Computer Architecture News, 2006