Design and analysis of a programmable single-chip architecture for DVB-T base-band receiver
- 22 December 2003
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 7 references indexed in Scilit:
- Parallel variable length decoding with inverse quantization for software MPEG-2 decodersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- An efficient method for simulation of frequency selective isotropic Rayleigh fadingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Optimum receiver design for OFDM-based broadband transmission .II. A case studyIEEE Transactions on Communications, 2001
- MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applicationsIEEE Transactions on Computers, 2000
- Design and Implementation of the MorphoSys Reconfigurable Computing ProcessorJournal of Signal Processing Systems, 2000
- DSP based OFDM demodulator and equalizer for professional DVB-T receiversIEEE Transactions on Broadcasting, 1999
- An area-efficient pipelined VLSI architecture for decoding of Reed-Solomon codes based on a time-domain algorithmIEEE Transactions on Circuits and Systems for Video Technology, 1997