Intermixing at the tantalum oxide/silicon interface in gate dielectric structures

Abstract

Metal oxides with high dielectric constants have the potential to extend scaling of transistor gate capacitance beyond that of ultrathin silicon dioxide. However, during deposition of most metal oxides on silicon, an interfacial region of ${\mathrm{SiO}}_x$ can form that limits the specific capacitance of the gate structure. We have examined the composition of this layer using high-resolution depth profiling of medium ion energy scattering combined with infrared spectroscopy and transmission electron microscopy. We find that the interfacial region is not pure ${\mathrm{SiO}}_{\mathrm{2}},$ but is a complex depth-dependent ternary oxide of ${\mathrm{Si–Ta}}_x–{\mathrm{O}}_y$ with a dielectric constant at least twice that of pure ${\mathrm{SiO}}_{\mathrm{2}}$ as inferred from electrical measurements. High-temperature annealing crystallizes the ${\mathrm{Ta}}_{\mathrm{2}}{\mathrm{O}}_{\mathrm{5}}$ film and converts the composite oxide to a more pure ${\mathrm{SiO}}_{\mathrm{2}}$ layer with a lower capacitance density. Using low postanneal temperatures, a stable composite oxide structure can be obtained with good electrical properties and an effective ${\mathrm{SiO}}_{\mathrm{2}}$ thickness of less than 2 nm with ∼10 nm of composite oxide.