Matching the Transconductance Characteristics of CMOS ISFET Arrays by Removing Trapped Charge
- 21 March 2008
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 55 (4), 1074-1079
- https://doi.org/10.1109/ted.2008.916680
Abstract
This paper presents an approach for matching the transconductance characteristics of CMOS ISFET arrays by removing trapped charge. We describe how to design arrays of floating-gate ISFETs so that ultraviolet (UV) radiation and bulk-substrate biasing can be used to remove the random amount of trapped charge that accumulates on the gates during fabrication. The approach is applied directly to a prototype single-chip 2 2 array of ISFETs, which is designed and fabricated in a standard 0.35- CMOS process. By considering the transconductance characteristics of the 2 2 array before and after UV exposure, it is shown that the response can be matched after 10 h and that the ISFET threshold voltages converge to an equilibrium value of approximately 1 V. After matching, it is found that the ISFET array has a measured sensitivity of 46 mV/pH and can successfully image a change in the pH of a homogeneous electrolyte solution.Keywords
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