ATPG for ultra-large structured designs
- 4 December 2002
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A ATPG (automatic test pattern generation) system that can efficiently create a high-coverage test for extremely large scan designs is described. This system is formed by optimally combining a fast fault simulator with a powerful test generator. For the ISCAS85 and ISCAS89 circuits, this ATPG system created a test for all testable faults and identified all redundant faults without a single aborted fault. This represents the first time this has been achieved for the ISCAS89 designs, and the performance of this ATPG system is significantly better than published results. Performing ATPG for the largest ISCAS89 designs, which contained about 25000 gates, required only 3 min of CPU time on an Apollo DN3550 workstation. The data collected for the ISCAS designs showed that the ATPG CPU time increased linearly with gate count. This strongly suggests that ATPG can be efficiently performed for circuits of 100000 and even one million gates.Keywords
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