Index Generation Functions: Minimization Methods
- 1 May 2017
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE) in 2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL)
- p. 197-206
- https://doi.org/10.1109/ismvl.2017.22
Abstract
Incompletely specified index generation functions can often be represented with fewer variables than original functions by appropriately assigning values to don't cares. The number of variables can be further reduced by using a linear transformation to the input variables. Minimization of variables under such conditions was considered to be a very hard problem. This paper surveys minimization methods for index generation functions. Major topics include 1) An upper bound on the number of variables to represent index generation functions,2) A heuristic minimization method using an ambiguity measure,3) A heuristic minimization method using remainders of a polynomial on GF(2),4) An exact minimization method using a SAT solver, and 5) Comparison of minimization methods.Keywords
This publication has 28 references indexed in Scilit:
- A Reduction Method for the Number of Variables to Represent Index Generation Functions: s-Min MethodPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2015
- Synthesis Algorithm for Parallel Index GeneratorIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2014
- A Method to Find Linear Decompositions for Incompletely Specified Index Generation Functions Using Difference MatrixIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2014
- An Application of Autocorrelation Functions to Find Linear Decompositions for Incompletely Specified Index Generation FunctionsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2013
- An Architecture for IPv6 Lookup Using Parallel Index Generation UnitsLecture Notes in Computer Science, 2013
- A Virus Scanning Engine Using an MPU and an IGU Based on Row-Shift DecompositionIEICE Transactions on Information and Systems, 2013
- Implementations of Reconfigurable Logic Arrays on FPGAsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2007
- Content-Addressable Memory (CAM) Circuits and Architectures: A Tutorial and SurveyIEEE Journal of Solid-State Circuits, 2006
- On the number of dependent variables for incompletely specified multiple-valued functionsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Design automation tools for efficient implementation of logic functions by decompositionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1989