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Formal Equivalence Checking and Design Debugging
Home
Publications
Formal Equivalence Checking and Design Debugging
Formal Equivalence Checking and Design Debugging
SH
Shi-Yu Huang
Shi-Yu Huang
KC
Kwang-Ting Cheng
Kwang-Ting Cheng
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1 January 1998
book
Published by
Springer Science and Business Media LLC
https://doi.org/10.1007/978-1-4615-5693-0
Abstract
No abstract available
Keywords
ASIC
RTL
ALGORITHMS
CIRCUIT
COMPUTER-AIDED DESIGN (CAD)
DEBUGGING
DIAGNOSIS
INTEGRATED CIRCUIT
LOGIC
MECHANICS
SIMULATION
SOFTWARE
VERIFICATION
Cited by 92 articles