500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC
Top Cited Papers
- 26 March 2007
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 42 (4), 739-747
- https://doi.org/10.1109/jssc.2007.892169
Abstract
A 500-MS/s 5-bit ADC for UWB applications has been fabricated in a 65-nm CMOS technology using no analog-specific processing options. The time-interleaved successive approximation register (SAR) architecture has been chosen due to its simplicity versus flash and its amenability to scaled technologies versus pipelined, which relies on operational amplifiers. Six time-interleaved channels are used, sharing a single clock operating at the composite sampling rate. Each channel has a split capacitor array that reduces switching energy, increases speed, and has similar INL and decreased DNL, as compared to a conventional binary-weighted array. A variable delay line adjusts the instant of latch strobing to reduce preamplifier currents. The ADC achieves Nyquist performance, with an SNDR of 27.8 and 26.1 dB for 3.3and 239 MHz inputs, respectively. The total active area is 0.9mm2, and the ADC consumes 6 mW from a 1.2-V supplyKeywords
This publication has 24 references indexed in Scilit:
- A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13-$\mu{\hbox{m}}$ CMOSIEEE Journal of Solid-State Circuits, 2006
- Dual scalable 500MS/s, 5b time-Interleaved SAR ADCs for UWB applicationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2006
- A 0.16pJ/Conversion-Step 2.5mW 1.25GS/s 4b ADC in a 90nm Digital CMOS ProcessPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2006
- A 6-bit 1.2-GS/s low-power flash-ADC in 0.13-/spl mu/m digital CMOSIEEE Journal of Solid-State Circuits, 2005
- A 1-GHz signal bandwidth 6-bit CMOS ADC with power-efficient averagingIEEE Journal of Solid-State Circuits, 2005
- A 6b 600MHz 10mW ADC array in digital 90nm CMOSPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2004
- A 6-b 1.6-Gsample/s flash ADC in 0.18-μm CMOS using averaging terminationIEEE Journal of Solid-State Circuits, 2002
- Transistor matching in analog CMOS applicationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 10-bit 5-MS/s successive approximation ADC cell used in a 70-MS/s ADC array in 1.2-μm CMOSIEEE Journal of Solid-State Circuits, 1994
- Time interleaved converter arraysIEEE Journal of Solid-State Circuits, 1980