System-Level Modeling and Design Using SysML and SystemC
- 1 September 2007
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
SysML, the dedicated system-level UML-based notations proposed by the OMG, is gaining a lot of momentum to be widely accepted by system-level designers. IEEE has standardized SystemC to gain the fame of being powerful at the system-level architectural design and verification. Building on both SystemC and SysML success, we have dedicated this research to study and prototype the automatic translation of SysML designs into SystemC models. This work is an attempt to accelerate the SoC design process by raising the abstraction level in an automated environment.Keywords
This publication has 5 references indexed in Scilit:
- A Methodology for Bridging the Gap between UML and CodesignPublished by Springer Science and Business Media LLC ,2006
- A UML 2.0 profile for SystemCPublished by Association for Computing Machinery (ACM) ,2005
- Why Systems-on-Chip Needs More UML like a Hole in the HeadPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- SystemC and the future of design languages: opportunities for users and researchPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2004
- An object-oriented design process for system-on-chip using UMLPublished by Association for Computing Machinery (ACM) ,2002