Racetrack memory cell array with integrated magnetic tunnel junction readout
- 1 December 2011
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE) in 2011 International Electron Devices Meeting
- p. 24.3.1-24.3.4
- https://doi.org/10.1109/iedm.2011.6131604
Abstract
In this paper, we report the first demonstration of CMOS-integrated racetrack memory. The devices measured are complete memory cells integrated into the back end of line of IBM 90 nm CMOS. We show good integration yield across 200 mm wafers. With magnetic field-assist, we demonstrate current-driven read and write operations on cells within a 256-cell CMOS-integrated array.Keywords
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