On multiple fault analysis in combinational circuits by means of Boolean difference

Abstract

The Boolean difference has proved to be an elegant mathematical concept in the study of single faults of a stuck-at nature in combinational logic circuits. Recently Ku and Masson have extended this tool of analysis to cover all possible multiple-fault situations of logic circuits as well. In this letter, we have considered the problem of multiple-fault analysis through the use of the Boolean difference and derived suitable expressions that give the set of test-input codes for the detection of all possible multiple faults of combinational circuits. The developed expressions are compact and simpler, in general, and require much less computation to mire at the test vectors, particularly in cases where the multiple faults of interest are specified. These expressions, like those of Ku and Masson, are useful when only k simultaneous faults or all faults up to and including k faults are to be considered.