Fully-parallel LUT-based (2048,1723) LDPC code decoder for FPGA
- 1 December 2012
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE) in 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)
Abstract
A good trade-off between performance and complexity is achieved if the min-sum algorithm with 2-bit non-uniform quantization is used to decode Low-Density Parity-Check codes. This paper proposes a method to design Variable Node Update (VNU) units based on Look-up tables suitable to design decoders for this algorithm. The method has been developed for the (2048,1723) LDPC code of the IEEE 802.3an standard and fully-parallel architectures have been implemented in a FPGA device. The results show that with the proposed method 35% area saving is achieved with respect to the use of the conventional VNU units.Keywords
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