Characterization of Upset-Induced Degradation of Error-Mitigated High-Speed I/O's Using Fault Injection on SRAM Based FPGAs
- 28 August 2006
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Nuclear Science
- Vol. 53 (4), 2076-2083
- https://doi.org/10.1109/TNS.2006.876510
Abstract
Fault-injection experiments on Virtex-IItrade FPGAs quantify failure and degradation modes in I/O channels incorporating triple module redundancy (TMR). With increasing frequency (to 100 MHz), full TMR under both I/O standards investigated (LVCMOS at 3.3V and 1.8V) shows more configuration bits have a measurable detrimental performance effect when in errorKeywords
This publication has 2 references indexed in Scilit:
- Dynamic testing of Xilinx Virtex-II field programmable gate array (FPGA) input/output blocks (IOBs)IEEE Transactions on Nuclear Science, 2004
- SEU mitigation testing of Xilinx Virtex II FPGAsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2004