Time domain modeling of lossy interconnects
- 1 May 2001
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Advanced Packaging
- Vol. 24 (2), 191-196
- https://doi.org/10.1109/6040.928754
Abstract
A new model for dielectric loss, suitable for time domain modeling of printed circuit boards, is proposed. The model is based on a physical relaxation model. Complete time domain modeling of skin effect and dielectric losses in FR-4 boards are demonstrated and experimentally verified. Finally, the developed model is used to predict that FR-4 boards are useful for data rates up to 10 Gb/s.Keywords
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