Trench storage node technology for gigabit DRAM generations
- 24 December 2002
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 2 references indexed in Scilit:
- A fully planarized 0.25 μm CMOS technology for 256 Mbit DRAM and beyondPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Selectivity and Si-load in deep trench etchingMicroelectronic Engineering, 1995