Throughput/Area-efficient ECC Processor Using Montgomery Point Multiplication on FPGA
- 13 July 2015
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems II: Express Briefs
- Vol. 62 (11), 1078-1082
- https://doi.org/10.1109/tcsii.2015.2455992
Abstract
High throughput while maintaining low resource is a key issue for elliptic curve cryptography (ECC) hardware implementations in many applications. In this brief, an ECC processor architecture over Galois fields is presented, which achieves the best reported throughput/area performance on field-programmable gate array (FPGA) to date. A novel segmented pipelining digit serial multiplier is developed to speed up ECC point multiplication. To achieve low latency, a new combined algorithm is developed for point addition and point doubling with careful scheduling. A compact and flexible distributed-RAM-based memory unit design is developed to increase speed while keeping area low. Further optimizations were made via timing constraints and logic level modifications at the implementation level. The proposed architecture is implemented on Virtex4 (V4), Virtex5 (V5), and Virtex7 (V7) FPGA technologies and, respectively, achieved throughout/slice figures of 19.65, 65.30, and 64.48 (10 6 /(Seconds × Slices)).Keywords
This publication has 13 references indexed in Scilit:
- Low-Complexity Digit-Serial and Scalable SPB/GPB Multipliers Over Large Binary Extension Fields Using (b,2)-Way Karatsuba DecompositionIEEE Transactions on Circuits and Systems I: Regular Papers, 2014
- Low area ECC implementation on FPGAPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2013
- Novel Architecture for Efficient FPGA Implementation of Elliptic Curve Cryptographic Processor Over ${\rm GF}(2^{163})$IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2013
- Low-Latency Digit-Serial Systolic Double Basis Multiplier over $\mbi GF{(2^m})$ Using Subquadratic Toeplitz Matrix-Vector Product ApproachIEEE Transactions on Computers, 2012
- Theoretical Modeling of Elliptic Curve Scalar Multiplier on LUT-Based FPGAs for Area and SpeedIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2012
- Efficient Elliptic Curve Point Multiplication Using Digit-Serial Binary Field OperationsIEEE Transactions on Industrial Electronics, 2012
- Efficient FPGA Implementations of Point Multiplication on Binary Edwards and Generalized Hessian Curves Using Gaussian Normal BasisIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2011
- A high performance ECC hardware implementation with instruction-level parallelism over GF(2163)Microprocessors and Microsystems, 2010
- Optimum Digit Serial GF(2^m) Multipliers for Curve-Based CryptographyIEEE Transactions on Computers, 2006
- A fast algorithm for computing multiplicative inverses in GF(2m) using normal basesInformation and Computation, 1988