A 12 b 80 MS/s pipelined ADC with bootstrapped digital calibration
- 28 September 2004
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 6 references indexed in Scilit:
- A 12-bit 20-MS/s pipelined ADC with nested digital background calibrationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2004
- A 12 b 75 MS/s pipelined ADC using open-loop residue amplificationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Digital background calibration of an algorithmic analog-to-digital converter using a simplified queueIEEE Journal of Solid-State Circuits, 2003
- A 12 b 65 MSample/s CMOS ADC with 82 dB SFDR at 120 MHzPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 15-b 1-Msample/s digitally self-calibrated pipeline ADCIEEE Journal of Solid-State Circuits, 1993
- Dynamic element matching for high-accuracy monolithic D/A convertersIEEE Journal of Solid-State Circuits, 1976