Secure Scan Techniques: A Comparison
- 10 July 2006
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
Designing secure ICs requires fulfilling many design rules in order to protect access to secret data. However, these security design requirements may be in opposition to test needs and testability improvement techniques that increase both observability and controllability. Nevertheless, secure chip designers cannot neglect the testability of their chip; a high quality production testing is primordial to ensure a good level of security since any faulty devices could induce major security vulnerability. In this paper, we present different techniques securing the scan chain technique and compare them to point out their pros and consKeywords
This publication has 2 references indexed in Scilit:
- Secure Scan: A Design-for-Test Architecture for Crypto ChipsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006
- Scan based side channel attack on dedicated hardware implementations of Data Encryption StandardPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005