Automatic Test Generation for Combinational Threshold Logic Networks
- 18 July 2008
- journal article
- research article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Vol. 16 (8), 1035-1045
- https://doi.org/10.1109/tvlsi.2008.2000671
Abstract
We propose an automatic test pattern generation (ATPG) framework for combinational threshold networks. The motivation behind this work lies in the fact that many emerging nanotechnologies, such as resonant tunneling diodes (RTDs), single electron transistor (SET), and quantum cellular automata (QCA), implement threshold logic. Consequently, there is a need to develop an ATPG methodology for this type of logic. We have built the first automatic test pattern generator and fault simulator for threshold logic which has been integrated on top of an existing computer-aided design (CAD) tool. These exploit new fault collapsing techniques we have developed for threshold networks. We perform fault modeling, backed by HSPICE simulations, to show that many cuts and shorts in RTD-based threshold gates are equivalent to stuck-at faults at the inputs and output of the gate. Experimental results with the MCNC benchmarks indicate that test vectors were found for all testable stuck-at faults in their threshold network implementations.Keywords
This publication has 18 references indexed in Scilit:
- A Test Generation Framework for Quantum Cellular Automata CircuitsIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2007
- Evaluation Methodology for Single Electron Encoded Threshold Logic GatesPublished by Springer Science and Business Media LLC ,2006
- Testing of Digital SystemsPublished by Cambridge University Press (CUP) ,2003
- Sequential circuit design using synthesis and optimizationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A linear threshold gate implementation in single electron technologyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A new RTD-FET logic familyProceedings of the IEEE, 1999
- High-speed and low-power operation of a resonant tunneling logic gate MOBILEIEEE Electron Device Letters, 1998
- 12 GHz clocked operation of ultralow power interband resonant tunneling diode pipelined logic gatesIEEE Journal of Solid-State Circuits, 1997
- InP-based high-performance monostable-bistable transition logic elements (MOBILEs) using integrated multiple-input resonant-tunneling devicesIEEE Electron Device Letters, 1996
- Logical devices implemented using quantum cellular automataJournal of Applied Physics, 1994