An area-efficient digital pulsewidth modulation architecture suitable for FPGA implementation
- 28 June 2005
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 3, 1412
- https://doi.org/10.1109/apec.2005.1453214
Abstract
This paper describes a digital pulsewidth modulator (DPWM) designed for FPGA implementation. A novel multi-output pulsewidth modulation scheme is introduced, as is a frequency calibration method suitable for use on FPGAs. The resulting architecture provides versatile output waveforms with high resolution, but with a small area requirement.Keywords
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