Si-cap-free SiGe p-channel FinFETs and gate-all-around transistors in a replacement metal gate process: Interface trap density reduction and performance improvement by high-pressure deuterium anneal

Abstract

We demonstrate Si-cap-free SiGe p-channel FinFETs and gate-all-around (GAA) FETs in a replacement metal gate (RMG) process, for Ge contents of 25% and 45%. We show that the performance of these devices is substantially improved by high-pressure (HP) deuterium (D₂) anneal, which is ascribed to a 2x reduction in interface trap density (D_IT). Furthermore, it is found that (1) TMAH treatment of SiGe prior to HK deposition and (2) HK post-deposition annealing (PDA) are beneficial for D_IT reduction as well, and that NBTI reliability is improved by both HP D₂ anneal and TMAH treatment.