An 800-MHz embedded DRAM with a concurrent refresh mode
- 13 June 2005
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 40 (6), 1377-1387
- https://doi.org/10.1109/jssc.2005.848019
Abstract
An 800-MHz embedded DRAM macro employs a memory cell utilizing a device from the 90-nm high-performance technology menu; a 2.2-nm gate oxide 1.5 V IO device. A concurrent refresh mode is designed to improve the memory utilization to over 99% for a 64 /spl mu/s data retention time. A concurrent refresh scheduler utilizes up-count and down-count registers to identify at least one array to be refreshed at every clock cycle, emulating a classical distributed refresh mode. A command multiplier employs low frequency phased clock signals to generate the clock, commands, and addresses at rates up to 4/spl times/ that of the tester frequency. The macro integrates masked redundancy allocation logic during at speed multibank test. The hardware results show a 312-MHz random access frequency and 800-MHz multibank frequency at 1.2 V, respectively.Keywords
This publication has 16 references indexed in Scilit:
- A 300MHz multi-banked, eDRAM macro featuring GND sense, bit-line twisting and direct reference cell writePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- An 800MHz embedded DRAM with a concurrent refresh modePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2004
- A 312MHz 16Mb random-cycle embedded DRAM macro with 73μW power-down mode for mobile applicationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2004
- A 500MHz multi-banked compilable DRAM macro with direct write and programmable pipeliningPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2004
- A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interfaceIEEE Journal of Solid-State Circuits, 2003
- A 2.9ns random access cycle embedded DRAM with a destructive-readPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A multimedia 32 b RISC microprocessor with 16 Mb DRAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Electrically programmable fuse (eFUSE) using electromigration in silicidesIEEE Electron Device Letters, 2002
- 1-GHz fully pipelined 3.7-ns address access time 8 k/spl times/1024 embedded synchronous DRAM macroIEEE Journal of Solid-State Circuits, 2000
- Dynamically shift-switched dataline redundancy suitable for DRAM macro with wide data busIEEE Journal of Solid-State Circuits, 2000