Ground bounce in digital VLSI circuits
- 9 July 2003
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Vol. 11 (2), 180-193
- https://doi.org/10.1109/tvlsi.2003.810785
Abstract
This paper is concerned with the analysis and optimization of the ground bounce in digital CMOS circuits. First, an analytical method for calculating the ground bounce is presented. The proposed method relies on accurate models of the short-channel MOS device and the chip-package interface parasitics. Next the effect of ground bounce on the propagation delay and the optimum tapering factor of a multistage buffer is discussed and a mathematical relationship for total propagation delay in the presence of the ground bounce is obtained. Effect of an on-chip decoupling capacitor on the ground bounce waveform and circuit speed is analyzed next and a closed form expression for the peak value of the differential-mode component of the ground bounce in terms of the on-chip decoupling capacitor is provided. Finally, a design methodology for controlling the switching times of the output drivers to minimize the ground bounce is presented.Keywords
This publication has 14 references indexed in Scilit:
- Capacitive coupling and quantized feedback applied to conventional CMOS technologyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A new analytic model of simultaneous switching noise in CMOS systemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Modeling CMOS gates driving RC interconnect loadsIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 2001
- Simultaneous switching noise analysis and low-bounce buffer designIEE Proceedings - Circuits, Devices and Systems, 2001
- Interconnect and circuit modeling techniques for full-chip power supply noise analysisIEEE Transactions on Components, Packaging, and Manufacturing Technology: Part B, 1998
- Effects of simultaneous switching noise on the tapered buffer designIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1997
- Accurate simultaneous switching noise estimation including velocity-saturation effectsIEEE Transactions on Components, Packaging, and Manufacturing Technology: Part B, 1996
- Clock skew optimization for ground bounce controlPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1996
- CMOS tapered bufferIEEE Journal of Solid-State Circuits, 1990
- CMOS Circuit Speed and Buffer OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987