A high performance 0.25 mu m CMOS technology

Abstract

A high-performance 0.25- mu m CMOS (complementary metal oxide semiconductor) technology with a reduced operating voltage of 2.5 V is presented. A loaded ring oscillator (NAND FI=FO=3. C/sub w/=0.2 pF) delay per stage of 280 ps achieved (W/sub eff//L/sub eff/=15 mu m/0.25 mu m), which is a 1.7 X improvement over 0.5- mu m CMOS technology. At shorter channel lengths (0.18 mu m), a CMOS stage delay of 38 ps for unloaded inverter ring oscillators and 185 ps for loaded NAND are demonstrated. A reduced operating voltage in the range of 2.2-2.5 V is chosen to optimize performance without compromising reliability. Shallow junctions with abrupt profiles are used to minimize device series resistance as well as gate-to-source/drain (S/D) overlap capacitance. Dural poly (n/sup +/ and p/sup +/) gates are used to avoid buried-channel operation pFETs, resulting in superior short-channel characteristics. Poly and S/D sheet resistances are lowered, using a thin salicide (TiSi/sub 2/) process.