Logic synthesis and circuit customization using extensive external don't-cares
- 1 May 2010
- journal article
- Published by Association for Computing Machinery (ACM) in ACM Transactions on Design Automation of Electronic Systems
- Vol. 15 (3), 1-24
- https://doi.org/10.1145/1754405.1754411
Abstract
Traditional digital circuit synthesis flows start from an HDL behavioral definition and assume that circuit functions are almost completely defined, making don't-care conditions rare. However, recent design methodologies do not always satisfy these assumptions. For instance, third-party IP blocks used in a system-on-chip are often overdesigned for the requirements at hand. By focusing only on the input combinations occurring in a specific application, one could resynthesize the system to greatly reduce its area and power consumption. Therefore we extend modern digital synthesis with a novel technique, called SWEDE, that makes use of extensive external don't-cares. In addition, we utilize such don't-cares present implicitly in existing simulation-based verification environments for circuit customization. Experiments indicate that SWEDE scales to large ICs with half-million input vectors and handles practical cases well.Keywords
This publication has 19 references indexed in Scilit:
- Automatic architecture refinement techniques for customizing processing elementsPublished by Association for Computing Machinery (ACM) ,2008
- Improving constant-coefficient multiplier verification by partial product identificationPublished by Association for Computing Machinery (ACM) ,2008
- Node Mergers in the Presence of Don't CaresPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2007
- SAT-Based Scalable Formal Verification SolutionsPublished by Springer Science and Business Media LLC ,2007
- Opportunities and challenges for better than worst-case designPublished by Association for Computing Machinery (ACM) ,2005
- Interpolation and SAT-Based Model CheckingLecture Notes in Computer Science, 2003
- SimpleScalar: an infrastructure for computer system modelingComputer, 2002
- The testability-preserving concurrent decomposition and factorization of Boolean expressionsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1992
- The transduction method-design of logic networks based on permissible functionsIEEE Transactions on Computers, 1989
- Linear reasoning. A new form of the Herbrand-Gentzen theoremThe Journal of Symbolic Logic, 1957