Synchronization, coherence, and event ordering in multiprocessors
- 1 February 1988
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in Computer
- Vol. 21 (2), 9-21
- https://doi.org/10.1109/2.15
Abstract
The problems addressed apply to both throughput-oriented and speedup-oriented multiprocessor systems, either at the user level or the operating-system level. basic definitions are provided. Communication and synchronization are briefly explained, and hardware-level and software-level synchronization mechanisms are discussed. The cache coherence problem is examined, and solutions are described. Strong and weak ordering of events is considered. The user interface is discussed.Keywords
This publication has 12 references indexed in Scilit:
- Correct memory operation of cache-based multiprocessorsPublished by Association for Computing Machinery (ACM) ,1987
- Cache coherence protocols: evaluation using a multiprocessor simulation modelACM Transactions on Computer Systems, 1986
- Memory access buffering in multiprocessorsACM SIGARCH Computer Architecture News, 1986
- Essential Issues in Multiprocessor SystemsComputer, 1985
- Concepts and Notations for Concurrent ProgrammingACM Computing Surveys, 1983
- Using cache memory to reduce processor-memory trafficPublished by Association for Computing Machinery (ACM) ,1983
- Cache MemoriesACM Computing Surveys, 1982
- High-Speed Multiprocessors and Compilation TechniquesIEEE Transactions on Computers, 1980
- How to Make a Multiprocessor Computer That Correctly Executes Multiprocess ProgramsIEEE Transactions on Computers, 1979
- A New Solution to Coherence Problems in Multicache SystemsIEEE Transactions on Computers, 1978