A parallel decoding algorithm of LDPC codes using CUDA
- 1 October 2008
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A parallel belief propagation algorithm for decoding low-density parity-check (LDPC) codes is presented in this paper based on Compute Unified Device Architecture (CUDA). As a new hardware and software architecture for addressing and managing computations, CUDA offers parallel data computing using the highly multithreaded coprocessor driven by very high memory bandwidth GPU. The parallel decoding algorithm, based on CUDA, allows that all bit-nodes or check-nodes work simultaneously, thus provides an efficient and fast way for implementing the decoder.Keywords
This publication has 6 references indexed in Scilit:
- Speeding up Mutual Information Computation Using NVIDIA CUDA HardwarePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2007
- A parallel LSI architecture for LDPC decoder improving message-passing schedulePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2006
- Parallel decoding architectures for low density parity check codesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Factor graphs and the sum-product algorithmIEEE Transactions on Information Theory, 2001
- Near Shannon limit performance of low density parity check codesElectronics Letters, 1996
- Low-Density Parity-Check CodesPublished by MIT Press ,1963