A Low-Jitter Fast-Locked All-Digital Phase-Locked Loop With Phase–Frequency-Error Compensation
- 18 September 2015
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Vol. 24 (5), 1984-1992
- https://doi.org/10.1109/tvlsi.2015.2470545
Abstract
The previous fast-locked all-digital phase-locked loop (ADPLL) usually suffers from large timing jitter due to the steep frequency transfer curve of its digitally controlled oscillator (DCO). This paper presents an ADPLL that possesses a coarse frequency selection function. All DCO frequency transfer curves of the ADPLL have gentle slopes. The ADPLL selects one transfer curve before acquisition. To fulfill the fast-acquisition requirement, the proposed ADPLL employs the phase-frequency-error compensation technique. In the acquisition mode, the phase-error compensator resolves the problem of phase-error accumulation. Meanwhile, the frequency-error compensator predicts a proper control code by calculating the cycle time difference between the reference clock and the derived signal fed back from the DCO. Therefore, the proposed ADPLL can compensate for the phase and the frequency errors simultaneously. The experimental results show that the proposed ADPLL possesses a fine-tuning acquisition within 5 reference clock cycles. After acquisition, the code updates in a fractional manner in the tracking mode to enhance the tracking jitter performance. The ADPLL output frequency ranges from 860 MHz to 1 GHz. The measured rms jitter is 1.31 ps at 1-GHz frequency.Keywords
Funding Information
- Ministry of Science and Technology, Taiwan (MOST 103-2221-E-011-059)
This publication has 21 references indexed in Scilit:
- Spur-Free Multirate All-Digital PLL for Mobile Phones in 65 nm CMOSIEEE Journal of Solid-State Circuits, 2011
- A Fast Phase Tracking ADPLL for Video Pixel Clock Generation in 65 nm CMOS TechnologyIEEE Journal of Solid-State Circuits, 2011
- A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time-to-Digital ConverterIEEE Journal of Solid-State Circuits, 2010
- A Dynamic Phase Error Compensation Technique for Fast-Locking Phase-Locked LoopsIEEE Journal of Solid-State Circuits, 2010
- A Two-Cycle Lock-In Time ADPLL Design Based on a Frequency Estimation AlgorithmIEEE Transactions on Circuits and Systems II: Express Briefs, 2010
- A Fast Locking All-Digital Phase-Locked Loop via Feed-Forward Compensation TechniqueIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2010
- All-Digital PLL With Ultra Fast SettlingIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 2007
- A Clock Generator With Cascaded Dynamic Frequency Counting Loops for Wide Multiplication Range ApplicationsIEEE Journal of Solid-State Circuits, 2006
- A Novel All-Digital PLL With Software Adaptive FilterIEEE Journal of Solid-State Circuits, 2004
- An all-digital PLL for frequency multiplication by 4 to 1022 with seven-cycle lock timeIEEE Journal of Solid-State Circuits, 2003