Path-delay fault diagnosis in non-scan sequential circuits with at-speed test application
- 7 November 2002
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 10 references indexed in Scilit:
- Efficient diagnosis of path delay faults in digital logic circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Critical path tracing in sequential circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A non-enumerative path delay fault simulator for sequential circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Scan latch design for delay testPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Delay Fault Testing for VLSI CircuitsPublished by Springer Science and Business Media LLC ,1998
- On variable clock methods for path delay testing of sequential circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1997
- A deductive technique for diagnosis of bridging faultsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1997
- Delay fault diagnosis in sequential circuits based on path tracingIntegration, 1995
- An advanced diagnostic method for delay faults in combinational faulty circuitsJournal of Electronic Testing, 1995
- Multiple Fault Diagnosis in Combinational Circuits Based on an Effect-Cause AnalysisIEEE Transactions on Computers, 1980