Multiple-gate SOI MOSFETs: device design guidelines
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- 1 December 2002
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 49 (12), 2222-2229
- https://doi.org/10.1109/ted.2002.805634
Abstract
This paper describes computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices. The concept of a triple-gate device with sidewalls extending into the buried oxide (hereby called a "/spl Pi/-gate" or "Pi-gate" MOSFET) is introduced. The Pi-gate device is simple to manufacture and offers electrical characteristics similar to the much harder to fabricate gate-all-around MOSFET. To explore the optimum design space for four different gate structures, simulations were performed with four variable device parameters: gate length, channel width, doping concentration, and silicon film thickness. The efficiency of the different gate structures is shown to be dependent of these parameters. The simulation results indicate that the the Pi-gate device is a very promising candidate for future nanometer MOSFET applications.Keywords
This publication has 27 references indexed in Scilit:
- A fully depleted lean-channel transistor (DELTA)-a novel vertical ultra thin SOI MOSFETPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channelPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- FD/DG-SOI MOSFET-a viable approach to overcoming the device scaling limitPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Pi-Gate SOI MOSFETIEEE Electron Device Letters, 2001
- From SOI materials to innovative devicesSolid-State Electronics, 2001
- The behavior of narrow-width SOI MOSFETs with MESA isolationIEEE Transactions on Electron Devices, 2000
- A simple model for threshold voltage of surrounding-gate MOSFET'sIEEE Transactions on Electron Devices, 1998
- Fully depleted dual-gated thin-film SOI P-MOSFETs fabricated in SOI islands with an isolated buried polysilicon backgateIEEE Electron Device Letters, 1996
- Deep-submicrometer channel design in silicon-on-insulator (SOI) MOSFET'sIEEE Electron Device Letters, 1994