Hoplite: Building austere overlay NoCs for FPGAs
- 1 September 2015
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE) in 2015 25th International Conference on Field Programmable Logic and Applications (FPL)
Abstract
Customized unidirectional, bufferless, deflection-routed torus networks can outperform classic, bidirectional, buffered mesh networks for single-flit-oriented FPGA applications by as much as 1.5× (best achievable throughputs for a 10×10 system) or 2.5× (allocating same FPGA resources to both NoCs) for uniform random traffic. We present Hoplite, an efficient, lightweight, fast FPGA overlay NoC that is designed to be small and compact by (1) eliminating input buffers, and (2) reducing the cost of switch crossbar that have traditionally limited speeds and imposed heavy resource costs in conventional FPGA overlay NoCs. We implement bufferless deflection routing cheaply, requiring the generation of only output multiplexer controls and no backpressure handshakes. Additionally, we use directional channels that help reduce crossbar cost by restricting the number of inputs to the crossbar to three instead of four. When compared to buffered mesh switches, FPGA-based deflection routers are ≈3.5× smaller (HLS-generated switch) and 2.5× faster (clock period) for 32b payloads. In a separate experiment, we hand-crafted a prototype RTL version of our switch with RLOCS that requires only 60 LUTs and 100 FFs per router and runs at 2.9 ns.Keywords
This publication has 9 references indexed in Scilit:
- Keynote 3 — The past and future of FPGA soft processorsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2014
- Design tradeoffs for hard and soft FPGA-based Networks-on-ChipPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2012
- FPGA optimized packet-switched NoC using split and merge primitivesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2012
- TOPAZ: An Open-Source Interconnection Network Simulator for Chip Multiprocessors and SupercomputersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2012
- CONNECTPublished by Association for Computing Machinery (ACM) ,2012
- Evaluating Bufferless Flow Control for On-chip NetworksPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2010
- Low-cost router microarchitecture for on-chip networksPublished by Association for Computing Machinery (ACM) ,2009
- Packet Switched vs. Time Multiplexed FPGA Overlay NetworksPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2006
- Route packets, net wiresPublished by Association for Computing Machinery (ACM) ,2001